1. Field
One or more embodiments described herein relate to a semiconductor memory device that compensates a difference of bit line interconnection resistance.
2. Description of the Related Art
A data processing system may use a dynamic random access memory (DRAM) as a work memory. A DRAM may include a plurality of memory cells formed by one access transistor and one storage capacitor. Each memory cell is connected to a bit line and a word line for performing read and write operations.
During a read operation, data stored in a memory cell is sensed by a bit line sense amplifier connected to a bit line pair including a bit line and a complementary bit line. Data sensed by the bit line sense amplifier is differentially transferred to a local sense amplifier by a column select transistor pair.